Deep Learning Accelerator Design and Optimization

UC Irvine, US

The primary goal of this project was to co-optimize hardware and dataflow for a deep learning accelerator to efficiently execute VGG16 and UNet models. The team focused on designing and optimizing hardware parameters and dataflow directives using MAESTRO to meet strict latency and energy constraints.

By experimenting with directive orders, optimizing cluster sizes, and balancing latency vs. energy trade-offs, the team successfully met project constraints for both deep learning models. The systematic approach allowed efficient execution on the designed accelerator, demonstrating scalability and adaptability across different neural networks.